Sciweavers

233 search results - page 38 / 47
» Balance Testing of Logic Circuits
Sort
View
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 1 months ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
FCCM
2007
IEEE
165views VLSI» more  FCCM 2007»
13 years 10 months ago
Sparse Matrix-Vector Multiplication Design on FPGAs
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...
Junqing Sun, Gregory D. Peterson, Olaf O. Storaasl...
PADS
2003
ACM
14 years 2 months ago
DVS: An Object-Oriented Framework for Distributed Verilog Simulation
There is a wide-spread usage of hardware design languages(HDL) to speed up the time-to-market for the design of modern digital systems. Verification engineers can simulate hardwa...
Lijun Li, Hai Huang, Carl Tropper
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
14 years 19 days ago
A synchronization algorithm for local temporal refinements in perfectly synchronous models with nested feedback loops
he abstract and simple computation and communication mechanism in the synchronous computational model it is easy to simulate synchronous systems and to apply formal verification m...
Tarvo Raudvere, Ingo Sander, Axel Jantsch
AAAI
1996
13 years 10 months ago
Qualitative Multiple-Fault Diagnosis of Continuous Dynamic Systems Using Behavioral Modes
Most model-based diagnosis systems, such as GDE and Sherlock, have concerned discrete, static systems such as logic circuits and use simple constraint propagation to detect incons...
Siddarth Subramanian, Raymond J. Mooney