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» Balance Testing of Logic Circuits
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TIME
2005
IEEE
14 years 2 months ago
LOLA: Runtime Monitoring of Synchronous Systems
Abstract— We present a specification language and algorithms for the online and offline monitoring of synchronous systems including circuits and embedded systems. Such monitori...
Ben D'Angelo, Sriram Sankaranarayanan, Césa...
DAC
2007
ACM
14 years 15 days ago
Side-Channel Attack Pitfalls
While cryptographic algorithms are usually strong against mathematical attacks, their practical implementation, both in software and in hardware, opens the door to side-channel at...
Kris Tiri
FPGA
2006
ACM
129views FPGA» more  FPGA 2006»
14 years 7 days ago
Power-aware RAM mapping for FPGA embedded memory blocks
Embedded memory blocks are important resources in contemporary FPGA devices. When targeting FPGAs, application designers often specify high-level memory functions which exhibit a ...
Russell Tessier, Vaughn Betz, David Neto, Thiagara...
WISES
2004
13 years 10 months ago
Embedded Real-Time-Tracer - An Approach with IDE
-- Debugging software that runs on highly integrated System-on-Chip devices is complicated because conventional debug tools (like traditional In-Circuit Emulators and Logic Analyze...
Babak Rahbaran, Matthias Függer, Andreas Stei...
ICCAD
2009
IEEE
96views Hardware» more  ICCAD 2009»
13 years 6 months ago
PSTA-based branch and bound approach to the silicon speedpath isolation problem
The lack of good "correlation" between pre-silicon simulated delays and measured delays on silicon (silicon data) has spurred efforts on so-called silicon debug. The ide...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm