1221 search results - page 107 / 245 » Balanced graph partitioning |
CLEIEJ
2010
13 years 7 months ago
2010
A 3D circuit is the stacking of regular 2D circuits. The advances on the fabrication and packaging technologies allowed interconnecting stacked 2D circuits by using 3D vias. Howeve...
ICASSP
2008
IEEE
14 years 4 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
ICASSP
2007
IEEE
14 years 4 months ago
2007
IEEE
This paper introduces a novel energy minimization method, namely iterated cross entropy with partition strategy (ICEPS), into the Markov random field theory. The solver, which is...
CC
2007
Springer
14 years 4 months ago
2007
Springer
This paper presents a compiler technique that reduces the energy consumption of the memory subsystem, for an off-chip partitioned memory architecture having multiple memory banks ...
AIEDAM
2007
13 years 10 months ago
2007
Achieving the dimensional integrity for a complex structural assembly is a demanding task due to the manufacturing variations of parts and the tolerance relationship between them....