Sciweavers

1221 search results - page 225 / 245
» Balanced graph partitioning
Sort
View
ASYNC
1998
IEEE
110views Hardware» more  ASYNC 1998»
13 years 12 months ago
Analyzing Specifications for Delay-Insensitive Circuits
We present the XDI Model for specifying delay-insensitive circuits, that is, reactive systems that correctly exchange signals with their environment in spite of unknown delays inc...
Tom Verhoeff
SPAA
1998
ACM
13 years 12 months ago
Elimination Forest Guided 2D Sparse LU Factorization
Sparse LU factorization with partial pivoting is important for many scienti c applications and delivering high performance for this problem is di cult on distributed memory machin...
Kai Shen, Xiangmin Jiao, Tao Yang
EUROPAR
1998
Springer
13 years 12 months ago
Parallel Sparse Matrix Computations Using the PINEAPL Library: A Performance Study
Abstract. The Numerical Algorithms Group Ltd is currently participating in the European HPCN Fourth Framework project on Parallel Industrial NumErical Applications and Portable Lib...
Arnold R. Krommer
SIGGRAPH
1994
ACM
13 years 11 months ago
IRIS performer: a high performance multiprocessing toolkit for real-time 3D graphics
This paper describes the design and implementation of IRIS Performer, a toolkit for visual simulation, virtual reality, and other real-time 3D graphics applications. The principal...
John Rohlf, James Helman
CP
2007
Springer
13 years 11 months ago
Efficient Computation of Minimal Point Algebra Constraints by Metagraph Closure
Abstract. Computing the minimal network (or minimal CSP) representation of a given set of constraints over the Point Algebra (PA) is a fundamental reasoning problem. In this paper ...
Alfonso Gerevini, Alessandro Saetti