55 search results - page 10 / 11 » Balancing Logic Utilization and Area Efficiency in FPGAs |
BMCBI
2008
13 years 7 months ago
2008
Background: This paper describes techniques for accelerating the performance of the string set matching problem with particular emphasis on applications in computational proteomic...
ANCS
2006
ACM
14 years 1 months ago
2006
ACM
The increase of the web traffic has created the need for web switches that are able to balance the traffic to the server farms based on their contents (e.g. layer 7 switching). In...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT ...
FPGA
2008
ACM
13 years 9 months ago
2008
ACM
Pattern-based synthesis has drawn wide interest from researchers who tried to utilize the regularity in applications for design optimizations. In this paper we present a general p...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...