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» Balancing Performance and Reliability in the Memory Hierarch...
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MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 1 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
ISCA
2009
IEEE
189views Hardware» more  ISCA 2009»
14 years 2 months ago
Hybrid cache architecture with disparate memory technologies
Caching techniques have been an efficient mechanism for mitigating the effects of the processor-memory speed gap. Traditional multi-level SRAM-based cache hierarchies, especially...
Xiaoxia Wu, Jian Li, Lixin Zhang, Evan Speight, Ra...
MASCOTS
1997
13 years 8 months ago
A Hybrid Simulation Approach Enabling Performance Characterization of Large Software Systems
We describe a method for performance analysis of large software systems that combines a fast instruction-set simulator with off-line detailed analysis of segments of the execution...
Bengt Werner, Peter S. Magnusson
JCPHY
2011
192views more  JCPHY 2011»
12 years 10 months ago
Fast analysis of molecular dynamics trajectories with graphics processing units - Radial distribution function histogramming
The calculation of radial distribution functions (RDFs) from molecular dynamics trajectory data is a common and computationally expensive analysis task. The rate limiting step in ...
Benjamin G. Levine, John E. Stone, Axel Kohlmeyer
DAC
2007
ACM
14 years 8 months ago
A Self-Tuning Configurable Cache
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
Ann Gordon-Ross, Frank Vahid