117 search results - page 21 / 24 » Balancing power consumption in multiprocessor systems |
CODES
2010
IEEE
13 years 5 months ago
2010
IEEE
The last years have shown that there is no way to disregard the advantages provided by multiprocessor System-on-Chip (MPSoC) architectures in the embedded systems domain. Using mu...
ICS
2005
Tsinghua U.
14 years 1 months ago
2005
Tsinghua U.
We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
SIES
2010
IEEE
13 years 5 months ago
2010
IEEE
Abstract--In distributed embedded systems operated by battery, energy management is a critical issue that has to be addressed at different architecture levels. For systems that tig...
ISPASS
2010
IEEE
14 years 2 months ago
2010
IEEE
—The ongoing move to chip multiprocessors (CMPs) permits greater sharing of last-level cache by processor cores but this sharing aggravates the cache contention problem, potentia...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
—In this paper, we propose a cost-effective and low-power 64-point fast Fourier transform (FFT)/inverse FFT (IFFT) architecture and chip adopting the retrenched 8-point FFT/IFFT ...