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HPCA
2005
IEEE
14 years 10 months ago
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
Youtao Zhang, Lan Gao, Jun Yang 0002, Xiangyu Zhan...
ASPLOS
2000
ACM
14 years 2 months ago
Architecture and design of AlphaServer GS320
This paper describes the architecture and implementation of the AlphaServer GS320, a cache-coherent non-uniform memory access multiprocessor developed at Compaq. The AlphaServer G...
Kourosh Gharachorloo, Madhu Sharma, Simon Steely, ...
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
14 years 2 months ago
Coherent Network Interfaces for Fine-Grain Communication
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hil...
CN
2007
105views more  CN 2007»
13 years 9 months ago
Flow-level QoS for a dynamic load of rate adaptive sessions sharing a bottleneck link
We consider the flow-level quality of service (QoS) seen by a dynamic load of rate adaptive sessions sharing a bottleneck link based on fair share bandwidth allocation. This is o...
Steven Weber, Gustavo de Veciana
INFOCOM
2003
IEEE
14 years 3 months ago
Evaluation of an Adaptive Transport Protocol
—Applications on mobile computers must adapt to high variability in wireless network performance. Extending the semantics of transport protocols to offer more control over commun...
Benjamin Atkin, Kenneth P. Birman