271 search results - page 14 / 55 » Bandwidth-Friendly Cache Hierarchy |
ASPLOS
1991
ACM
14 years 1 months ago
1991
ACM
Blocking is a well-known optimization technique for improving the effectiveness of memory hierarchies. Instead of operating on entire rows or columns of an array, blocked algorith...
DATE
2005
IEEE
14 years 3 months ago
2005
IEEE
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
ICS
2005
Tsinghua U.
14 years 3 months ago
2005
Tsinghua U.
We present a cache oblivious algorithm for stencil computations, which arise for example in finite-difference methods. Our algorithm applies to arbitrary stencils in n-dimension...
DAC
2007
ACM
14 years 11 months ago
2007
ACM
The memory hierarchy of a system can consume up to 50% of microprocessor system power. Previous work has shown that tuning a configurable cache to a particular application can red...
ISCA
2007
IEEE
14 years 4 months ago
2007
IEEE
The ever increasing sizes of on-chip caches and the growing domination of wire delay necessitate significant changes to cache hierarchy design methodologies. Many recent proposal...