271 search results - page 16 / 55 » Bandwidth-Friendly Cache Hierarchy |
IEEEPACT
2003
IEEE
14 years 3 months ago
2003
IEEE
We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the numb...
IPPS
1998
IEEE
14 years 2 months ago
1998
IEEE
The increasing gap in processor and memory speeds has forced microprocessors to rely on deep cache hierarchies to keep the processors from starving for data. For many applications...
EUROPAR
2000
Springer
14 years 1 months ago
2000
Springer
With the increasing processing power, the latency of the memory hierarchy becomes the stumbling block of many modern computer architectures. In order to speed-up the calculations, ...
GECCO
2009
Springer
13 years 7 months ago
2009
Springer
Simultaneous Multithreading (SMT) is a technology aimed at improving the throughput of the processor core by applying Instruction Level Parallelism (ILP) and Thread Level Parallel...
CIDR
2007
13 years 11 months ago
2007
We propose a radical approach to relational query processing that aims at automatically and consistently achieving a good performance on any memory hierarchy. We believe this auto...