271 search results - page 25 / 55 » Bandwidth-Friendly Cache Hierarchy |
DCC
2008
IEEE
13 years 11 months ago
2008
IEEE
Researchers have proposed using hardware data compression units within the memory hierarchies of microprocessors in order to improve performance, energy efficiency, and functional...
SIGMETRICS
2005
ACM
14 years 3 months ago
2005
ACM
The running time of many applications is dominated by the cost of memory operations. To optimize such applications for a given platform, it is necessary to have a detailed knowled...
VALUETOOLS
2006
ACM
14 years 3 months ago
2006
ACM
Cache locality optimization is an efficient way for reducing the idle time of modern processors in waiting for needed data. This kind of optimization can be achieved either on the...
IEEEPACT
2005
IEEE
14 years 3 months ago
2005
IEEE
This paper presents a new technique for efficient usage of small trace caches. A trace cache can significantly increase the performance of wide out-oforder processors, but to be e...
IWSOC
2003
IEEE
14 years 3 months ago
2003
IEEE
: - A filter cache is proposed at a higher level than the L1 (main) cache in the memory hierarchy and is much smaller. The typical size of filter cache is of the order of 512 Bytes...