271 search results - page 39 / 55 » Bandwidth-Friendly Cache Hierarchy |
LCPC
2005
Springer
14 years 3 months ago
2005
Springer
There is growing interest in autonomic computing systems that can optimize their own behavior on different platforms without manual intervention. Examples of successful self-opti...
TC
2008
13 years 9 months ago
2008
To support dynamic address translation in today's microprocessors, the first-level cache is accessed in parallel with a translation lookaside buffer (TLB). However, this curre...
MICRO
2006
IEEE
14 years 3 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
ASAP
2006
IEEE
13 years 11 months ago
2006
IEEE
In today's embedded systems, memory hierarchy is rapidly becoming a major factor in terms of power, performance and area. This is especially true for embedded multimedia appl...
IPPS
2010
IEEE
13 years 7 months ago
2010
IEEE
Abstract--The now commonplace multi-core chips have introduced, by design, a deep hierarchy of memory and cache banks within parallel computers as a tradeoff between the user frien...