2 search results - page 1 / 1 » Behavioral synthesis with activating unused flip-flops for r... |
ASPDAC
2008
ACM
13 years 10 months ago
2008
ACM
FPGA
2010
ACM
14 years 5 months ago
2010
ACM
Guarded evaluation is a power reduction technique that involves identifying sub-circuits (within a larger circuit) whose inputs can be held constant (guarded) at specific times d...