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    » Being Bayesian about Network Structure
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    ICCV
    2007
    IEEE
    227views Computer Vision» more  ICCV 2007»
    COST: An Approach for Camera Selection and Multi-Object Inference Ordering in Dynamic Scenes
    13 years 11 months ago
    COST: An Approach for Camera Selection and Multi-Object Inference Ordering in Dynamic Scenes
    Download  www.cse.iitm.ac.in
    Development of multiple camera based vision systems for analysis of dynamic objects such as humans is challenging due to occlusions and similarity in the appearance of a person wi...
    Abhinav Gupta, Anurag Mittal, Larry S. Davis
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    UAI
    2004
    134views Artificial Intelligence» more  UAI 2004»
    Dependent Dirichlet Priors and Optimal Linear Estimators for Belief Net Parameters
    13 years 11 months ago
    Dependent Dirichlet Priors and Optimal Linear Estimators for Belief Net Parameters
    Download  www.stat.ualberta.ca
    A Bayesian belief network is a model of a joint distribution over a finite set of variables, with a DAG structure representing immediate dependencies among the variables. For each...
    Peter Hooper
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    UAI
    1997
    133views Artificial Intelligence» more  UAI 1997»
    Score and Information for Recursive Exponential Models with Incomplete Data
    13 years 11 months ago
    Score and Information for Recursive Exponential Models with Incomplete Data
    Download  research.microsoft.com
    Recursive graphical models usually underlie the statistical modelling concerning probabilistic expert systems based on Bayesian networks. This paper de nes a version of these mode...
    Bo Thiesson
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    WCE
    2007
    106views Electrical And Computer Engi...» more  WCE 2007»
    Wavepackets in the Recognition of Isolated Handwritten Characters
    13 years 11 months ago
    Wavepackets in the Recognition of Isolated Handwritten Characters
    Download  www.iaeng.org
    — This work is to apply wavelet packet transformation for the recognition of isolated handwritten Malayalam (one of the south Indian languages) characters. The key idea is that c...
    G. Raju, K. Revathy
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    ICCAD
    2000
    IEEE
    109views Hardware» more  ICCAD 2000»
    Latency-Guided On-Chip Bus Network Design
    14 years 2 months ago
    Latency-Guided On-Chip Bus Network Design
    Download  research.microsoft.com
    Abstract— Deep submicron technology scaling has two major ramifications on the design process. First, reduced feature size significantly increases wire delay, thus resulting in...
    Milenko Drinic, Darko Kirovski, Seapahn Meguerdich...
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