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ISLPED
1999
ACM
150views Hardware» more  ISLPED 1999»
13 years 12 months ago
Using dynamic cache management techniques to reduce energy in a high-performance processor
In this paper, we propose a technique that uses an additional mini cache, the L0-Cache, located between the instruction cache I-Cache and the CPU core. This mechanism can provid...
Nikolaos Bellas, Ibrahim N. Hajj, Constantine D. P...
HPDC
1999
IEEE
13 years 12 months ago
Overview of a Performance Evaluation System for Global Computing Scheduling Algorithms
While there have been several proposals of high performance global computing systems, scheduling schemes for the systems have not been well investigated. The reason is difficultie...
Atsuko Takefusa, Satoshi Matsuoka, Hidemoto Nakada...
CC
1999
Springer
107views System Software» more  CC 1999»
13 years 12 months ago
Link-Time Improvement of Scheme Programs
Abstract. Optimizing compilers typically limit the scope of their analyses and optimizations to individual modules. This has two drawbacks: rst, library code cannot be optimized to...
Saumya K. Debray, Robert Muth, Scott A. Watterson
COMPULOG
1999
Springer
13 years 12 months ago
Decomposable Constraints
Many constraint satisfaction problems can be naturally and efficiently modelled using non-binary constraints like the “all-different” and “global cardinality” constraints...
Ian P. Gent, Kostas Stergiou, Toby Walsh
RTSS
1999
IEEE
13 years 12 months ago
Timing Anomalies in Dynamically Scheduled Microprocessors
Previous timing analysis methods have assumed that the worst-case instruction execution time necessarily corresponds to the worst-case behavior. We show that this assumption is wr...
Thomas Lundqvist, Per Stenström