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» Benchmarking Anomaly-Based Detection Systems
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ICFP
2007
ACM
14 years 6 months ago
Feedback directed implicit parallelism
In this paper we present an automated way of using spare CPU resources within a shared memory multi-processor or multi-core machine. Our approach is (i) to profile the execution o...
Tim Harris, Satnam Singh
ISCA
2009
IEEE
146views Hardware» more  ISCA 2009»
14 years 1 months ago
Multi-execution: multicore caching for data-similar executions
While microprocessor designers turn to multicore architectures to sustain performance expectations, the dramatic increase in parallelism of such architectures will put substantial...
Susmit Biswas, Diana Franklin, Alan Savage, Ryan D...
CGO
2008
IEEE
14 years 1 months ago
Prediction and trace compression of data access addresses through nested loop recognition
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
Alain Ketterlin, Philippe Clauss
MTV
2007
IEEE
121views Hardware» more  MTV 2007»
14 years 26 days ago
Chico: An On-chip Hardware Checker for Pipeline Control Logic
The widening gap between CPU complexity and verification capability is becoming increasingly more salient. It is impossible to completely verify the functionality of a modern mic...
Andrew DeOrio, Adam Bauserman, Valeria Bertacco
RTCSA
2007
IEEE
14 years 26 days ago
A Real-Time Database Testbed and Performance Evaluation
A lot of real-time database (RTDB) research has been done to process transactions in a timely fashion using fresh data reflecting the current real world status. However, most exi...
Kyoung-Don Kang, Phillip H. Sin, Jisu Oh