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FCCM
2007
IEEE
129views VLSI» more  FCCM 2007»
14 years 4 months ago
Automatic On-chip Memory Minimization for Data Reuse
FPGA-based computing engines have become a promising option for the implementation of computationally intensive applications due to high flexibility and parallelism. However, one...
Qiang Liu, George A. Constantinides, Konstantinos ...
3DPVT
2006
IEEE
183views Visualization» more  3DPVT 2006»
14 years 3 months ago
High-Quality Real-Time Stereo Using Adaptive Cost Aggregation and Dynamic Programming
We present a stereo algorithm that achieves high quality results while maintaining real-time performance. The key idea is simple: we introduce an adaptive aggregation step in a dy...
Liang Wang, Miao Liao, Minglun Gong, Ruigang Yang,...
CGO
2003
IEEE
14 years 2 months ago
Speculative Register Promotion Using Advanced Load Address Table (ALAT)
The pervasive use of pointers with complicated patterns in C programs often constrains compiler alias analysis to yield conservative register allocation and promotion. Speculative...
Jin Lin, Tong Chen, Wei-Chung Hsu, Pen-Chung Yew
CLUSTER
2009
IEEE
14 years 2 months ago
Finding a tradeoff between host interrupt load and MPI latency over Ethernet
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...
Brice Goglin, Nathalie Furmento
INFOCOM
1999
IEEE
14 years 1 months ago
Design and Performance of a Web Server Accelerator
We describe the design, implementation and performance of a Web server accelerator which runs on an embedded operating system and improves Web server performance by caching data. ...
Eric Levy-Abegnoli, Arun Iyengar, Junehwa Song, Da...