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» Benchmarking and hardware implementation of JPEG-LS
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ISCAS
2011
IEEE
261views Hardware» more  ISCAS 2011»
12 years 11 months ago
Hardware synchronization for embedded multi-core processors
Abstract— Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers shou...
Christian Stoif, Martin Schoeberl, Benito Liccardi...
PDP
2005
IEEE
14 years 1 months ago
A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol
SVM systems are a cheaper and flexible way to implement the shared memory programming paradigm. Their huge flexibility is due to their software implementation; however, this is al...
Salvador Petit, Julio Sahuquillo, Ana Pont
CIMAGING
2009
94views Hardware» more  CIMAGING 2009»
13 years 5 months ago
Iterative demosaicking accelerated: theory and fast noniterative implementations
Color image demosaicking is a key process in the digital imaging pipeline. In this paper, we present a rigorous treatment of a classical demosaicking algorithm based on alternatin...
Yue M. Lu, Mina Karzand, Martin Vetterli
ICCAD
2005
IEEE
93views Hardware» more  ICCAD 2005»
14 years 4 months ago
Eliminating wire crossings for molecular quantum-dot cellular automata implementation
— When exploring computing elements made from technologies other than CMOS, it is imperative to investigate the effects of physical implementation constraints. This paper focuses...
Amitabh Chaudhary, Danny Z. Chen, Kevin Whitton, M...
MICRO
2010
IEEE
202views Hardware» more  MICRO 2010»
13 years 2 months ago
Hardware Support for Relaxed Concurrency Control in Transactional Memory
Today's transactional memory systems implement the two-phase-locking (2PL) algorithm which aborts transactions every time a conflict happens. 2PL is a simple algorithm that pr...
Utku Aydonat, Tarek S. Abdelrahman