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FMCAD
2009
Springer
14 years 2 months ago
Mixed abstractions for floating-point arithmetic
stractions for Floating-Point Arithmetic Angelo Brillout Computer Systems Institute, ETH Zurich Daniel Kroening and Thomas Wahl Oxford University Computing Laboratory Abstract—Fl...
Angelo Brillout, Daniel Kroening, Thomas Wahl
CATS
2008
13 years 9 months ago
Generating Balanced Parentheses and Binary Trees by Prefix Shifts
We show that the set Bn of balanced parenthesis strings with n left and n right parentheses can be generated by prefix shifts. If b1, b2, . . . , b2n is a member of Bn, then the k...
Frank Ruskey, Aaron Williams
ISMVL
2008
IEEE
148views Hardware» more  ISMVL 2008»
14 years 1 months ago
Quantum Logic Implementation of Unary Arithmetic Operations
The mathematical property of inheritance for certain unary fixed point operations has recently been exploited to enable the efficient formulation of arithmetic algorithms and circ...
Mitchell A. Thornton, David W. Matula, Laura Spenn...
FPGA
2008
ACM
155views FPGA» more  FPGA 2008»
13 years 9 months ago
A novel FPGA logic block for improved arithmetic performance
To improve FPGA performance for arithmetic circuits, this paper proposes a new architecture for FPGA logic cells that includes a 6:2 compressor. The new cell features additional f...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
APCSAC
2003
IEEE
14 years 23 days ago
Arithmetic Circuits Combining Residue and Signed-Digit Representations
This paper discusses the use of signed-digit representations in the implementation of fast and efficient residue-arithmetic units. Improvements to existing signed-digit modulo adde...
Anders Lindström, Michael Nordseth, Lars Beng...