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IEEEPACT
2009
IEEE
14 years 3 months ago
Data Layout Transformation for Enhancing Data Locality on NUCA Chip Multiprocessors
—With increasing numbers of cores, future CMPs (Chip Multi-Processors) are likely to have a tiled architecture with a portion of shared L2 cache on each tile and a bankinterleave...
Qingda Lu, Christophe Alias, Uday Bondhugula, Thom...
CORR
2007
Springer
154views Education» more  CORR 2007»
13 years 8 months ago
Application of a design space exploration tool to enhance interleaver generation
This paper presents a methodology to efficiently explore the design space of communication adapters. In most digital signal processing (DSP) applications, the overall performance ...
Cyrille Chavet, Philippe Coussy, Pascal Urard, Eri...
BMCBI
2010
156views more  BMCBI 2010»
13 years 9 months ago
Adaptive coarse-grained Monte Carlo simulation of reaction and diffusion dynamics in heterogeneous plasma membranes
Background: An adaptive coarse-grained (kinetic) Monte Carlo (ACGMC) simulation framework is applied to reaction and diffusion dynamics in inhomogeneous domains. The presented mod...
Stuart Collins, Michail Stamatakis, Dionisios G. V...
DAS
2008
Springer
13 years 10 months ago
Difference of Boxes Filters Revisited: Shadow Suppression and Efficient Character Segmentation
A robust segmentation is the most important part of an automatic character recognition system (e.g. document processing, license plate recognition etc.). In our contribution we pr...
Erik Rodner, Herbert Süße, Wolfgang Ort...
IEEEPACT
2006
IEEE
14 years 2 months ago
Testing implementations of transactional memory
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi...