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VLSID
2006
IEEE
136views VLSI» more  VLSID 2006»
14 years 7 months ago
Improved Data Compression for Serial Interconnected Network on Chip through Unused Significant Bit Removal
Serial links in network on chip provide advantages in terms of reduced wiring area, reduced switch complexity and power. However, serial links offer lower bandwidth in comparison ...
Simon Ogg, Bashir M. Al-Hashimi
ERSA
2010
159views Hardware» more  ERSA 2010»
13 years 4 months ago
Acceleration of FPGA Fault Injection Through Multi-Bit Testing
SRAM-based FPGA devices are an attractive option for data processing on space-based platforms, due to high computational capabilities and a lower power envelope than traditional pr...
Grzegorz Cieslewski, Alan D. George, Adam Jacobs
CGO
2006
IEEE
13 years 10 months ago
Space-Efficient 64-bit Java Objects through Selective Typed Virtual Addressing
Memory performance is an important design issue for contemporary systems given the ever increasing memory gap. This paper proposes a space-efficient Java object model for reducing...
Kris Venstermans, Lieven Eeckhout, Koen De Bossche...
JSAC
2008
118views more  JSAC 2008»
13 years 6 months ago
PEEC: a channel-adaptive feedback-based error
Reliable transmission is a challenging task over wireless LANs since wireless links are known to be susceptible to errors. Although the current IEEE802.11 standard ARQ error contro...
Sohraab Soltani, Hayder Radha
GI
2005
Springer
14 years 6 days ago
Trust and quality in electronic communication: Getting to know your customers bit by bit
: A client was experiencing trust and information quality problems in his structured Internet communication with potential and existing customers. Customer information entered onli...
Andreas Neus, Philipp Scherf, Christian Gebert