We propose an organization for the on-chip memory system of a chip multiprocessor, in which 16 processors share a 16MB pool of 256 L2 cache banks. The L2 cache is organized as a n...
Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhan...
The present paper continues the study (begun by Quattrocchi, Colouring 4-cycle systems with specified block colour pattern: the case of embedding P3-designs, Electron. J. Combin.,...
Terry S. Griggs, Giovanni Lo Faro, Gaetano Quattro...
Conventional cache models are not suited for real-time parallel processing because tasks may flush each other’s data out of the cache in an unpredictable manner. In this way th...
Anca Mariana Molnos, Marc J. M. Heijligers, Sorin ...
A non-blocking protocol that allows real-time tasks to share data in a multiprocessor system is presented in this paper. The protocol gives the means to concurrent real-time tasks...