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RTCSA
1999
IEEE
14 years 29 days ago
A Method to Improve the Estimated Worst-Case Performance of Data Caching
This paper presents a method for tight prediction of worst-case performance of data caches in highperformance real-time systems. Our approach is to distinguish between data struct...
Thomas Lundqvist, Per Stenström
FAST
2010
13 years 11 months ago
Extending SSD Lifetimes with Disk-Based Write Caches
We present Griffin, a hybrid storage device that uses a hard disk drive (HDD) as a write cache for a Solid State Device (SSD). Griffin is motivated by two observations: First, HDD...
Gokul Soundararajan, Vijayan Prabhakaran, Mahesh B...
FDL
2004
IEEE
14 years 12 days ago
Real-Time Operating System Services for Realistic SystemC Simulation Models of Embedded Systems
gn process of embedded systems moves currently towards higher levels of abstraction. As a consequence, a need arises for an early and realistic assessment of system level design d...
P. Hastono, Stephan Klaus, Sorin A. Huss
DATE
2007
IEEE
99views Hardware» more  DATE 2007»
14 years 3 months ago
Instruction trace compression for rapid instruction cache simulation
Modern Application Specific Instruction Set Processors (ASIPs) have customizable caches, where the size, associativity and line size can all be customized to suit a particular ap...
Andhi Janapsatya, Aleksandar Ignjatovic, Sri Param...
MAM
2006
126views more  MAM 2006»
13 years 8 months ago
HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems
Embedded systems are typically heterogeneous requiring interacting hardware and software components, are locally synchronous while being globally asynchronous and combine both con...
Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza...