613 search results - page 92 / 123 » Block cache for embedded systems |
WORDS
2002
IEEE
14 years 15 days ago
2002
IEEE
The Worst-Case Execution-Time Analysis (WCET Analysis) of program code that is to be executed on modern processors is a highly complex task. First, it involves path analysis, to i...
RTAS
1998
IEEE
13 years 12 months ago
1998
IEEE
Static timing analyzers need to know the minimum and maximum number of iterations associated with each loop in a real-time program so accurate timing predictions can be obtained. ...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
—Networks-on-Chip (NoCs) have appeared as design strategy to overcome the limitations, in terms of scalability, efficiency, and power consumption of current buses. In this paper...
JCIT
2010
13 years 2 months ago
2010
We consider an M/G/1 queue with general retrial times where the blocked customers may balk the system, or join the priority queue, or enter the orbit. As soon as a customer is ser...
CASE
2011
12 years 7 months ago
2011
— Legacy systems that do not conform to the norms and regulations imposed by recent safety standards have to be upgraded to meet safety requirements. In this paper, we describe a...