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2006
IEEE
14 years 3 months ago
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
Martijn Coenen, Srinivasan Murali, Andrei Radulesc...
FCCM
2006
IEEE
113views VLSI» more  FCCM 2006»
14 years 3 months ago
GraphStep: A System Architecture for Sparse-Graph Algorithms
— Many important applications are organized around long-lived, irregular sparse graphs (e.g., data and knowledge bases, CAD optimization, numerical problems, simulations). The gr...
Michael DeLorimier, Nachiket Kapre, Nikil Mehta, D...
FCCM
2006
IEEE
133views VLSI» more  FCCM 2006»
14 years 3 months ago
A Field Programmable RFID Tag and Associated Design Flow
Current Radio Frequency Identification (RFID) systems generally have long design times and low tolerance to changes in specification. This paper describes a field programmable,...
Alex K. Jones, Raymond R. Hoare, Swapna R. Donthar...
GLOBECOM
2006
IEEE
14 years 3 months ago
Packet Delay-Aware Scheduling in Input Queued Switches
Abstract— Virtual Output Queuing is widely used by highspeed packet switches to overcome head-of-line blocking. This is done by means of matching algorithms. In fixed-length VOQ...
Yihan Li, Shivendra S. Panwar, H. Jonathan Chao, J...
GLOBECOM
2006
IEEE
14 years 3 months ago
Interleaved Multistage Switching Fabrics for Scalable High Performance Routers
As the Internet grows exponentially, scalable high performance routers and switches on backbone are required to provide a large number of ports, higher throughput, lower delay late...
Rongsen He, José G. Delgado-Frias
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