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VLSID
2006
IEEE
121views VLSI» more  VLSID 2006»
14 years 8 months ago
An Integrated Approach for Combining BDD and SAT Provers
Many formal verification tools today are based on Boolean proof techniques. The two most powerful approaches in this context are Binary Decision Diagrams (BDDs) and methods based ...
Rolf Drechsler, Görschwin Fey, Sebastian Kind...
TCAD
2008
96views more  TCAD 2008»
13 years 7 months ago
An Implicit Approach to Minimizing Range-Equivalent Circuits
Abstract--Simplifying a combinational circuit while preserving its range has a variety of applications, such as combinational equivalence checking and random simulation. Previous a...
Yung-Chih Chen, Chun-Yao Wang
TABLEAUX
1998
Springer
13 years 12 months ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin
VSTTE
2005
Springer
14 years 1 months ago
Model Checking: Back and Forth between Hardware and Software
The interplay back and forth between software model checking and hardware model checking has been fruitful for both. Originally intended for the analysis of concurrent software, mo...
Edmund M. Clarke, Anubhav Gupta, Himanshu Jain, He...
ETS
2010
IEEE
150views Hardware» more  ETS 2010»
13 years 8 months ago
Improving CNF representations in SAT-based ATPG for industrial circuits using BDDs
It was shown in the past that ATPG based on the Boolean Satisfiability problem is a beneficial complement to traditional ATPG techniques. Its advantages can be observed especially ...
Daniel Tille, Stephan Eggersglüß, Rene ...