Sciweavers

125 search results - page 9 / 25
» Boolean Satisfiability with Transitivity Constraints
Sort
View
ACSD
2004
IEEE
113views Hardware» more  ACSD 2004»
14 years 1 months ago
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of...
Victor Khomenko, Maciej Koutny, Alexandre Yakovlev
TCS
2008
13 years 9 months ago
Verification of qualitative Z constraints
We introduce an LTL-like logic with atomic formulae built over a constraint language interpreting variables in Z. The constraint language includes periodicity constraints, comparis...
Stéphane Demri, Régis Gascon
VLSID
2002
IEEE
177views VLSI» more  VLSID 2002»
14 years 10 months ago
RTL-Datapath Verification using Integer Linear Programming
Satisfiability of complex word-level formulas often arises as a problem in formal verification of hardware designs described at the register transfer level (RTL). Even though most...
Raik Brinkmann, Rolf Drechsler
LPAR
2005
Springer
14 years 3 months ago
Deciding Separation Logic Formulae by SAT and Incremental Negative Cycle Elimination
Separation logic is a subset of the quantifier-free first order logic. It has been successfully used in the automated verification of systems that have large (or unbounded) inte...
Chao Wang, Franjo Ivancic, Malay K. Ganai, Aarti G...
CORR
2008
Springer
90views Education» more  CORR 2008»
13 years 10 months ago
A Pseudo-Boolean Solution to the Maximum Quartet Consistency Problem
Determining the evolutionary history of a given biological data is an important task in biological sciences. Given a set of quartet topologies over a set of taxa, the Maximum Quart...
António Morgado, João P. Marques Sil...