Sciweavers

11 search results - page 3 / 3
» Boolean factoring and decomposition of logic networks
Sort
View
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
13 years 11 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...