Sciweavers

799 search results - page 142 / 160
» Bound Performance Models of Heterogeneous Parallel Processin...
Sort
View
153
Voted
IPPS
2006
IEEE
15 years 9 months ago
FPGA implementation of a license plate recognition SoC using automatically generated streaming accelerators
Modern FPGA platforms provide the hardware and software infrastructure for building a bus-based System on Chip (SoC) that meet the applications requirements. The designer can cust...
Nikolaos Bellas, Sek M. Chai, Malcolm Dwyer, Dan L...
152
Voted
ECRTS
2008
IEEE
15 years 10 months ago
Backlog Estimation and Management for Real-Time Data Services
Real-time data services can benefit data-intensive real-time applications, e.g., e-commerce, via timely transaction processing using fresh data, e.g., the current stock prices. T...
Kyoung-Don Kang, Jisu Oh, Yan Zhou
127
Voted
ACSAC
2009
IEEE
15 years 10 months ago
SecureMR: A Service Integrity Assurance Framework for MapReduce
—MapReduce has become increasingly popular as a powerful parallel data processing model. To deploy MapReduce as a data processing service over open systems such as service orient...
Wei Wei, Juan Du, Ting Yu, Xiaohui Gu
139
Voted
HIPEAC
2007
Springer
15 years 9 months ago
A Throughput-Driven Task Creation and Mapping for Network Processors
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-C...
142
Voted
SPAA
2005
ACM
15 years 9 months ago
Value-maximizing deadline scheduling and its application to animation rendering
We describe a new class of utility-maximization scheduling problem with precedence constraints, the disconnected staged scheduling problem (DSSP). DSSP is a nonpreemptive multipro...
Eric Anderson, Dirk Beyer 0002, Kamalika Chaudhuri...