493 search results - page 26 / 99 » Bounded LTL Model Checking with Stable Models |
GLVLSI
2009
IEEE
14 years 2 months ago
2009
IEEE
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
MTV
2003
IEEE
14 years 28 days ago
2003
IEEE
Bounded Model Checking (BMC) techniques have been used for formal hardware verification, with the help of tools such as GRASP (Generic search Algorithm for Satisfiability Proble...
ENTCS
2006
13 years 7 months ago
2006
Increasing attention has been paid recently to criteria that allow one to conclude that a structure models a linear-time property from the knowledge that no counterexamples exist ...
ATVA
2007
Springer
14 years 1 months ago
2007
Springer
This paper presents a bounded model checking algorithm for the verification of analog and mixed-signal (AMS) circuits using a satisfiability modulo theories (SMT) solver. The sys...
CHARME
2003
Springer
14 years 27 days ago
2003
Springer
We consider the problem of bounded model checking of systems expressed in a decidable fragment of first-order logic. While model checking is not guaranteed to terminate for an ar...