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» Bounded Model Checking with Description Logic Reasoning
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CADE
2008
Springer
14 years 9 months ago
Towards SMT Model Checking of Array-Based Systems
Abstract. We introduce the notion of array-based system as a suittraction of infinite state systems such as broadcast protocols or sorting programs. By using a class of quantified-...
Silvio Ghilardi, Enrica Nicolini, Silvio Ranise, D...
DAC
1998
ACM
14 years 9 months ago
Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability
Abstract-Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model des...
Farzan Fallah, Srinivas Devadas, Kurt Keutzer
DLOG
2011
13 years 11 days ago
Relaxed Abduction: Robust Information Interpretation for Incomplete Models
This paper introduces relaxed abduction, a novel non-standard reasoning task for description logics. Although abductive reasoning over description logic knowledge bases has been ap...
Thomas Hubauer, Steffen Lamparter, Michael Pirker
LICS
2006
IEEE
14 years 2 months ago
PSPACE Bounds for Rank-1 Modal Logics
aic semantics, which conveniently abstracts from the details of a given model class and thus allows covering a broad range of logics in a uniform way. Categories and Subject Descri...
Lutz Schröder, Dirk Pattinson
LFCS
2007
Springer
14 years 3 months ago
Model Checking Knowledge and Linear Time: PSPACE Cases
We present a general algorithm scheme for model checking logics of knowledge, common knowledge and linear time, based on simulations to a class of structures that capture the way t...
Kai Engelhardt, Peter Gammie, Ron van der Meyden