616 search results - page 7 / 124 » Bounded Model Checking with Description Logic Reasoning |
CADE
2006
Springer
14 years 9 months ago
2006
Springer
This is a system description of the Description Logic reasoner FaCT++. The reasoner implements a tableaux decision procedure for the well known SHOIQ description logic, with additi...
DLOG
2008
13 years 11 months ago
2008
In this paper we consider the extensions of description logics that were proposed to represent uncertain or vague knowledge, focusing on the fuzzy and possibilistic formalisms. We ...
ASPDAC
2007
ACM
14 years 29 days ago
2007
ACM
This paper presents a Boolean based symbolic model checking algorithm for the verification of analog/mixedsignal (AMS) circuits. The systems are modeled in VHDL-AMS, a hardware des...
DLOG
2004
13 years 10 months ago
2004
DLOG
1996
13 years 10 months ago
1996