135 search results - page 2 / 27 » Bounded Synthesis |
ISSS
2000
IEEE
13 years 11 months ago
2000
IEEE
This paper addresses the problem of estimating lower bounds on the power consumption in scheduled data flow graphs with a fixed number of allocated resources prior to binding. T...
FMCAD
2009
Springer
14 years 1 months ago
2009
Springer
Abstract—Dynamically allocated and manipulated data structures cannot be translated into hardware unless there is an upper bound on the amount of memory the program uses during a...
FMICS
2006
Springer
13 years 11 months ago
2006
Springer
Abstract. In this paper, we concentrate on incremental synthesis of timed automata for automatic addition of different types of bounded response properties. Bounded response
DATE
2003
IEEE
14 years 19 days ago
2003
IEEE
: Binary Decision Diagrams (BDDs) have been widely used in synthesis and verification. Boolean Satisfiability (SAT) Solvers, on the other hand, have been gaining
AUTOMATICA
2004
13 years 7 months ago
2004
This paper deals with feedback controller synthesis for timed event graphs in dioids, where the number of initial tokens and time delays are only known to belong to intervals. We ...