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» Bounded-lifetime integrated circuits
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ISCAS
2005
IEEE
132views Hardware» more  ISCAS 2005»
14 years 2 months ago
AER EAR: a matched silicon cochlea pair with address event representation interface
In this paper we present an analog integrated circuit containing a matched pair of silicon cochleae and an address event interface. Each section of the cochlea, modeled by a secon...
André van Schaik, Shih-Chii Liu
MICRO
2006
IEEE
159views Hardware» more  MICRO 2006»
13 years 8 months ago
MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, Will...
ICCAD
1993
IEEE
121views Hardware» more  ICCAD 1993»
14 years 17 days ago
Hierarchical extraction of 3D interconnect capacitances in large regular VLSI structures
For submicron integrated circuits, 3D numerical techniques are required to accurately compute the values of the interconnect capacitances. In this paper, we describe an hierarchic...
Arjan J. van Genderen, N. P. van der Meijs
HOST
2009
IEEE
14 years 7 days ago
New Design Strategy for Improving Hardware Trojan Detection and Reducing Trojan Activation Time
Hardware Trojans in integrated circuits and systems have become serious concern to fabless semiconductor industry and government agencies in recent years. Most of the previously p...
Hassan Salmani, Mohammad Tehranipoor, Jim Plusquel...
IPPS
2010
IEEE
13 years 5 months ago
Prototype for a large-scale static timing analyzer running on an IBM Blue Gene
This paper focuses on parallelization of the classic static timing analysis (STA) algorithm for verifying timing characteristics of digital integrated circuits. Given ever-increasi...
Akintayo Holder, Christopher D. Carothers, Kerim K...