23 search results - page 2 / 5 » Bounding Worst-Case Instruction Cache Performance |
HIPEAC
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. High end routers are targeted at providing worst case throughput guarantees over latency. Caches on the other hand are meant to help latency not throughput in a tradition...
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Caches are notorious for their unpredictability. It is difficult or even impossible to predict if a memory access results in a definite cache hit or miss. This unpredictability i...
STOC
2006
ACM
14 years 1 months ago
2006
ACM
Memory management is a fundamental problem in computer architecture and operating systems. We consider a two-level memory system with fast, but small cache and slow, but large mai...
RTSS
2003
IEEE
14 years 27 days ago
2003
IEEE
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
VLDB
2004
ACM
14 years 29 days ago
2004
ACM
Online transaction processing (OLTP) is a multibillion dollar industry with high-end database servers employing state-of-the-art processors to maximize performance. Unfortunately,...