We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serv...
This paper describes the implementation of a runtime library for asynchronous communication in the Cell BE processor. The runtime library implementation provides with several servi...
This paper describes the design, implementation, and experimental evaluation of OverQoS, an overlay-based architecture for enhancing the best-effort service of today's Intern...
Lakshminarayanan Subramanian, Ion Stoica, Hari Bal...
In this paper we introduce the Range Trie, a new multiway tree data structure for address lookup. Each Range Trie node maps to an address range [Na, Nb) and performs multiple comp...
Ioannis Sourdis, Georgios Stefanakis, Ruben de Sme...
— The need for efficient counter architecture has arisen for the following two reasons. Firstly, a number of data streaming algorithms and network management applications requir...