An FPGA architecture for DRAM-based systolic computations

We propose an FPGA chip architecture based on a conventional FPGA logic array core, in which I/O pins are clocked at a much higher rate than that of the logic array that they serve. Wide data paths within the chip are time multiplexed at the edge of the chip into much faster and narrower data paths that run offchip. This kind of arrangement makes it possible to interface a relatively slow FPGA core with high speed memories and data streams, and is useful for many pin-limited FPGA applications. For efficient use of the highest bandwidth DRAM’s, our proposed chip includes a RAMBUS DRAM interface, a burst-transfer controller, and burst buffers. This proposal is motivated by our work with virtual processor cellular automata (CA) machines—a kind of SIMD computer. Our next generation of CA machines requires reconfigurable FPGA-like processors coupled to the highest speed DRAM’s and SRAM’s available. Unfortunately, no current FPGA chips have appropriate DRAM I/O support or the spe...

• Type: Conference
• Year: 1997
• Where: FCCM
• Authors: Norman Margolus
• Keywords: Chips, FCCM 1997, FPGA, Fpga Chips, VLSI