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RTSS
2003
IEEE
14 years 28 days ago
Experimental Evaluation of Code Properties for WCET Analysis
This paper presents a quantification of the timing effects that advanced processor features like data and instruction cache, pipelines, branch prediction units and out-oforder ex...
Antoine Colin, Stefan M. Petters
ISCA
1999
IEEE
87views Hardware» more  ISCA 1999»
13 years 12 months ago
Dynamic Vectorization: A Mechanism for Exploiting Far-Flung ILP in Ordinary Programs
Several ILP limit studies indicate the presence of considerable ILP across dynamically far-apart instructions in program execution. This paper proposes a hardware mechanism, dynam...
Sriram Vajapeyam, P. J. Joseph, Tulika Mitra
ISCA
1998
IEEE
135views Hardware» more  ISCA 1998»
13 years 12 months ago
Confidence Estimation for Speculation Control
Modern processors improve instruction level parallelism by speculation. The outcome of data and control decisions is predicted, and the operations are speculatively executed and o...
Dirk Grunwald, Artur Klauser, Srilatha Manne, Andr...
ISCA
1998
IEEE
125views Hardware» more  ISCA 1998»
13 years 12 months ago
Performance Characterization of a Quad Pentium Pro SMP using OLTP Workloads
Commercial applications are an important, yet often overlooked, workload with significantly different characteristics from technical workloads. The potential impact of these diffe...
Kimberly Keeton, David A. Patterson, Yong Qiang He...
ISCAPDCS
2003
13 years 9 months ago
Loop Transformation Techniques To Aid In Loop Unrolling and Multithreading
In modern computer systems loops present a great deal of opportunities for increasing Instruction Level and Thread Level Parallelism. Loop unrolling is a technique used to obtain ...
Litong Song, Yuhua Zhang, Krishna M. Kavi