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ICCAD
2006
IEEE
108views Hardware» more  ICCAD 2006»
14 years 4 months ago
Soft error reduction in combinational logic using gate resizing and flipflop selection
Soft errors in logic are emerging as a significant reliability problem for VLSI designs. This paper presents novel circuit optimization techniques to mitigate soft error rates (SE...
Rajeev R. Rao, David Blaauw, Dennis Sylvester
ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Frequency Selective Model Order Reduction via Spectral Zero Projection
As process technology continues to scale into the nanoscale regime, interconnect plays an ever increasing role in determining VLSI system performance. As the complexity of these sy...
Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud
GECCO
2008
Springer
158views Optimization» more  GECCO 2008»
13 years 8 months ago
Objective reduction using a feature selection technique
This paper introduces two new algorithms to reduce the number of objectives in a multiobjective problem by identifying the most conflicting objectives. The proposed algorithms ar...
Antonio López Jaimes, Carlos A. Coello Coel...
ICDCS
2003
IEEE
14 years 23 days ago
A Generic Distributed Broadcast Scheme in Ad Hoc Wireless Networks
—We propose a generic framework for distributed broadcasting in ad hoc wireless networks. The approach is based on selecting a small subset of nodes to form a forward node set to...
Jie Wu, Fei Dai
ICSM
2005
IEEE
14 years 1 months ago
Test Suite Reduction with Selective Redundancy
Software testing is a critical part of software development. Test suite sizes may grow significantly with subsequent modifications to the software over time. Due to time and res...
Dennis Jeffrey, Neelam Gupta