68 search results - page 5 / 14 » Buffered Crossbar Fabrics Based on Networks on Chip |
ASAP
2003
IEEE
14 years 28 days ago
2003
IEEE
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
WCE
2007
13 years 8 months ago
2007
— Crossbars are main components of communication switches used to construct interconnection networks. Scheduling algorithm controls contention in switch architecture. Several sch...
SIGCOMM
2004
ACM
14 years 1 months ago
2004
ACM
−Buffered multistage interconnection networks offer one of the most scalable and cost-effective approaches to building high capacity routers. Unfortunately, the performance of su...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
Many System-on-a-Chip devices would benefit from the inclusion of reprogrammable logic on the silicon die, as it can add general computing ability, provide run-time reconfigurabil...
HOTI
2008
IEEE
14 years 2 months ago
2008
IEEE
Much of high performance technical computing has moved from shared memory architectures to message based cluster systems. The development and wide adoption of the MPI parallel pro...