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» Building the functional performance model of a processor
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CODES
2009
IEEE
14 years 1 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
13 years 6 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
SAC
2010
ACM
14 years 3 months ago
Adaptive internet services through performance and availability control
Cluster-based multi-tier systems provide a means for building scalable Internet services. Building adaptive Internet services that are able to apply appropriate system sizing and ...
Jean Arnaud, Sara Bouchenak
LCPC
2004
Springer
14 years 2 months ago
Branch Strategies to Optimize Decision Trees for Wide-Issue Architectures
Abstract. Branch predictors are associated with critical design issues for nowadays instruction greedy processors. We study two important domains where the optimization of decision...
Patrick Carribault, Christophe Lemuet, Jean-Thomas...
ASPDAC
2007
ACM
108views Hardware» more  ASPDAC 2007»
14 years 19 days ago
Software Performance Estimation in MPSoC Design
- Estimation tools are a key component of system-level methodologies, enabling a fast design space exploration. Estimation of software performance is essential in current software-...
Márcio Oyamada, Flávio Rech Wagner, ...