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» Building the functional performance model of a processor
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DATE
2010
IEEE
121views Hardware» more  DATE 2010»
14 years 1 months ago
Cost modeling and cycle-accurate co-simulation of heterogeneous multiprocessor systems
—In this paper, we present a method to analyze different implementations of stream-based applications on heterogeneous multiprocessor systems. We take both resource usage and per...
Sven van Haastregt, Eyal Halm, Bart Kienhuis
APCSAC
2006
IEEE
14 years 2 months ago
A High Performance Simulator System for a Multiprocessor System Based on a Multi-way Cluster
In the ubiquitous era, it is necessary to research the architectures of multiprocessor system with high performance and low power consumption. A simulator developed in high level l...
Arata Shinozaki, Masatoshi Shima, Minyi Guo, Mitsu...
SBACPAD
2008
IEEE
170views Hardware» more  SBACPAD 2008»
14 years 3 months ago
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
James Poe, Chang-Burm Cho, Tao Li
ISPASS
2007
IEEE
14 years 2 months ago
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world ap...
Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad ...
JOIN
2007
96views more  JOIN 2007»
13 years 8 months ago
Universal Routing and Performance Assurance for Distributed Networks
In this paper, we show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. W...
Kevin F. Chen, Edwin Hsing-Mean Sha