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» Building the functional performance model of a processor
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CODES
1999
IEEE
14 years 29 days ago
How standards will enable hardware/software co-design
o much higher levels of abstraction than today's design practices, which are usually at the level of synthesizable RTL for custom hardware or Instruction Set Simulator (ISS) f...
Mark Genoe, Christopher K. Lennard, Joachim Kunkel...
ASPLOS
2011
ACM
13 years 7 days ago
NV-Heaps: making persistent objects fast and safe with next-generation, non-volatile memories
nt, user-defined objects present an attractive abstraction for working with non-volatile program state. However, the slow speed of persistent storage (i.e., disk) has restricted ...
Joel Coburn, Adrian M. Caulfield, Ameen Akel, Laur...
CODES
2007
IEEE
14 years 3 months ago
Reliable multiprocessor system-on-chip synthesis
This article presents a multiprocessor system-on-chip synthesis (MPSoC) algorithm that optimizes system mean time to failure. Given a set of directed acyclic periodic graphs of co...
Changyun Zhu, Zhenyu (Peter) Gu, Robert P. Dick, L...
NAR
2006
156views more  NAR 2006»
13 years 8 months ago
VOMBAT: prediction of transcription factor binding sites using variable order Bayesian trees
Variable order Markov models and variable order Bayesian trees have been proposed for the recognition of transcription factor binding sites, and it could be demonstrated that they...
Jan Grau, Irad E. Ben-Gal, Stefan Posch, Ivo Gross...
SSDBM
2008
IEEE
177views Database» more  SSDBM 2008»
14 years 3 months ago
Prioritized Evaluation of Continuous Moving Queries over Streaming Locations
Abstract. Existing approaches to the management of streaming positional updates generally assume that all active user requests have equal importance, ignoring the possibility of an...
Kostas Patroumpas, Timos K. Sellis