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» C Compiler Design for an Industrial Network Processor
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ASPDAC
2008
ACM
145views Hardware» more  ASPDAC 2008»
13 years 10 months ago
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches
- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
Minje Jun, Sungjoo Yoo, Eui-Young Chung
MST
2000
101views more  MST 2000»
13 years 8 months ago
Robust Parallel Computations through Randomization
In this paper we present an efficient general simulation strategy for computations designed for fully operational BSP machines of n ideal processors, on n-processor dynamic-fault-p...
Spyros C. Kontogiannis, Grammati E. Pantziou, Paul...
CONCURRENCY
2000
83views more  CONCURRENCY 2000»
13 years 8 months ago
Javia: A Java interface to the virtual interface architecture
The Virtual Interface (VI) architecture has become the industry standard for user-level network interfaces. This paper presents the implementation and evaluation of Javia, a Java ...
Chi-Chao Chang, Thorsten von Eicken
IPPS
2007
IEEE
14 years 2 months ago
Optimizing the Fast Fourier Transform on a Multi-core Architecture
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
Long Chen, Ziang Hu, Junmin Lin, Guang R. Gao
GLOBECOM
2009
IEEE
14 years 3 months ago
A Simulation Study of CSMA/CA Performance in 60 GHz WPANs
— Recently, there has been an increasing interest in developing 60 GHz wireless personal area networks (WPANs) for short-range high-speed wireless communications. Both industrial...
Wei Zhou, Sai Shankar Nandagopalan, Daji Qiao