- We present a topology synthesis method for high performance System-on-Chip (SoC) design. Our method provides an optimal topology of on-chip communication network for the given ba...
In this paper we present an efficient general simulation strategy for computations designed for fully operational BSP machines of n ideal processors, on n-processor dynamic-fault-p...
Spyros C. Kontogiannis, Grammati E. Pantziou, Paul...
The Virtual Interface (VI) architecture has become the industry standard for user-level network interfaces. This paper presents the implementation and evaluation of Javia, a Java ...
The rapid revolution in microprocessor chip architecture due to multicore technology is presenting unprecedented challenges to the application developers as well as system softwar...
— Recently, there has been an increasing interest in developing 60 GHz wireless personal area networks (WPANs) for short-range high-speed wireless communications. Both industrial...