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ICCAD
2001
IEEE
184views Hardware» more  ICCAD 2001»
16 years 3 months ago
CALiBeR: A Software Pipelining Algorithm for Clustered Embedded VLIW Processors
In this paper we describe a software pipelining framework, CALiBeR (Cluster Aware Load Balancing Retiming Algorithm), suitable for compilers targeting clustered embedded VLIW proc...
Cagdas Akturan, Margarida F. Jacome
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
16 years 3 months ago
Single-Pass Redundancy Addition and Removal
Redundancy-addition-and-removal is a rewiring technique which for a given target wire wt finds a redundant alternative wire wa. Addition of wa makes wt redundant and hence removab...
Chih-Wei Jim Chang, Malgorzata Marek-Sadowska
ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
16 years 3 months ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...
ICCAD
2001
IEEE
152views Hardware» more  ICCAD 2001»
16 years 3 months ago
Hybrid Structured Clock Network Construction
This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating f...
Haihua Su, Sachin S. Sapatnekar
ICCAD
2001
IEEE
108views Hardware» more  ICCAD 2001»
16 years 3 months ago
Placement Driven Retiming with a Coupled Edge Timing Model
Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear, whether the pred...
Ingmar Neumann, Wolfgang Kunz