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DAGSTUHL
2007
14 years 11 days ago
Parallelism through Digital Circuit Design
Abstract. Two ways to exploit chips with a very large number of transistors are multicore processors and programmable logic chips. Some data parallel algorithms can be executed eï¬...
John O'Donnell
EH
2003
IEEE
138views Hardware» more  EH 2003»
14 years 4 months ago
Implementing Evolution of FIR-Filters Efficiently in an FPGA
Reconfigurable hardware devices make it possible to change the topology of electronic circuits at runtime. Using reconfigurable devices as a platform for Evolvable hardware (EHW) ...
Knut Arne Vinger, Jim Torresen
DATE
2009
IEEE
141views Hardware» more  DATE 2009»
14 years 2 months ago
Evaluation on FPGA of triple rail logic robustness against DPA and DEMA
Side channel attacks are known to be efficient techniques to retrieve secret data. In this context, this paper concerns the evaluation of the robustness of triple rail logic agains...
Victor Lomné, Philippe Maurine, Lionel Torr...
RECONFIG
2008
IEEE
268views VLSI» more  RECONFIG 2008»
14 years 5 months ago
Parametric, Secure and Compact Implementation of RSA on FPGA
1 We present a fast, efficient, and parameterized modular multiplier and a secure exponentiation circuit especially intended for FPGAs on the low end of the price range. The desig...
Ersin Oksuzoglu, Erkay Savas
FPL
2004
Springer
93views Hardware» more  FPL 2004»
14 years 4 months ago
The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays
This paper investigates experimentally the quantitative impact of pipelining on energy per operation for two representative FPGA devices: a 0.13µm CMOS high density/high speed FPG...
Steven J. E. Wilton, Su-Shin Ang, Wayne Luk