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FPL
2009
Springer
104views Hardware» more  FPL 2009»
14 years 2 months ago
A multi-layered XML schema and design tool for reusing and integrating FPGA IP
Reconfigurable computing systems remain difficult to use and program. One way to increase design productivity for these systems is through reuse of previously developed and veri...
Adam Arnesen, Nathan Rollins, Michael J. Wirthlin
FPT
2005
IEEE
131views Hardware» more  FPT 2005»
14 years 3 months ago
Dynamic Voltage Scaling for Commercial FPGAs
A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, ...
DSD
2005
IEEE
105views Hardware» more  DSD 2005»
14 years 3 months ago
Improved Fault Emulation for Synchronous Sequential Circuits
Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subta...
Jaan Raik, Peeter Ellervee, Valentin Tihhomirov, R...
IJCNN
2000
IEEE
14 years 2 months ago
Hardware Implementation of a PCA Learning Network by an Asynchronous PDM Digital Circuit
We have fabricated a PCA (Principal Component Analysis) learning network in a FPGA (Field Programmable Gate Array) by using an asynchronous PDM (Pulse Density Modulation) digital ...
Yuzo Hirai, Kuninori Nishizawa
IPPS
2006
IEEE
14 years 3 months ago
Securing embedded programmable gate arrays in secure circuits
The purpose of this article is to propose a survey of possible approaches for implementing embedded reconfigurable gate arrays into secure circuits. A standard secure interfacing ...
Nicolas Valette, Lionel Torres, Gilles Sassatelli,...