Securing embedded programmable gate arrays in secure circuits

The purpose of this article is to propose a survey of possible approaches for implementing embedded reconfigurable gate arrays into secure circuits. A standard secure interfacing architecture is proposed and motivations justifying such an approach are discussed. This paper also lists all features offered by FPGA vendors (Field Programmable Gate Array) aiming at securing those circuits according to different concerns. This article emphasizes on configuration memory programming which is probably the weakest point of using programmable devices on a secure context.

• Type: Conference
• Year: 2006
• Where: IPPS
• Authors: Nicolas Valette, Lionel Torres, Gilles Sassatelli, Frédéric Bancel
• Keywords: Distributed And Parallel Computing, Embedded Reconfigurable Gate, Field Programmable Gate Array, Gate Array, IPPS 2006