416 search results - page 57 / 84 » CMOL FPGA circuits |
FPGA
2000
ACM
14 years 1 months ago
2000
ACM
In this paper we introduce a new Simulated Annealingbased timing-driven placement algorithm for FPGAs. This paper has three main contributions. First, our algorithm employs a nove...
FPGA
2008
ACM
13 years 11 months ago
2008
ACM
Application-Specific Instruction-set Processors (ASIP) can improve execution speed by using custom instructions. Several ASIP design automation flows have been proposed recently. ...
TCAD
2008
13 years 9 months ago
2008
BDDs have proven to be an efficient means to represent and manipulate Boolean formulae [1] and sets [2] due to their compactness and canonicality. In this work, we leverage the eff...
TVLSI
2008
13 years 9 months ago
2008
This paper describes Glitchless, a circuit-level technique for reducing power in FPGAs by eliminating unnecessary logic transitions called glitches. This is done by adding program...
FPGA
2004
ACM
14 years 3 months ago
2004
ACM
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...