22 search results - page 4 / 5 » CMOS Comparators for High-Speed and Low-Power Applications |
GLVLSI
2007
IEEE
14 years 1 months ago
2007
IEEE
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
CORR
2010
Springer
13 years 4 months ago
2010
Springer
Reversible logic design has become one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power...
CORR
2010
Springer
13 years 2 months ago
2010
Springer
Combinational or Classical logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its correspon...
ASPDAC
2006
ACM
14 years 1 months ago
2006
ACM
— Sakurai-Newton (SN) delay metric [1] is a widely used closed form delay metric for CMOS gates because of simplicity and reasonable accuracy. Nevertheless it can be shown that t...
SOCC
2008
IEEE
14 years 1 months ago
2008
IEEE
In this paper a new ultra low power SRAM cell is proposed. In the proposed SRAM topology, additional circuitry has been added to a standard 6T-SRAM cell to improve the static nois...